The present invention relates to implementing a user logic design in a programmable logic device (PLD or, alternatively, FPGA), and more particularly, the present invention relates to implementing logic design memory in blocks that share logic and memory and physical memory devices of a programmable logic device.
Programmable logic devices are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved by “blowing” (i.e., opening) fusible links. Alternatively, the configuration may have been stored in a programmable read-only memory. Those devices generally provided the user with the ability to configure the devices for “sum-of-products” (or “P TERM”) logic operations. Later, such programmable logic devices incorporating erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which also can be reconfigured, store their configuration in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provide the user with the ability to configure the devices for look-up-table-type logic operations. At some point, such devices began to be provided with embedded blocks of random access memory that could be configured by the user to act as random access memory, read-only memory, or logic (such as P TERM logic).
Programmable logic devices are becoming more sophisticated with respect to, for example, the types of memory devices that they provide. This offers users the flexibility of designing logic without the previous limitation of being restricted to implementing that logic using a single type of memory device.
While it may have been possible to program the earliest programmable logic devices manually, simply by determining mentally where various elements should be laid out, it was common even in connection with such earlier devices to provide programming software that allowed a user to lay out logic as desired and then translate that logic into programming for the programmable logic device. With current larger devices, it would be impractical to attempt to lay out the logic without such software.
In certain conventional devices that utilize only physical memory clustering algorithms have typically packed user logical RAMs—i.e., memory requested in the user design or otherwise requested in a suitable design request—into one or more physical RAMs on the PLD. Because these algorithms were based on the devices that had only physical memory types, a single-pass packing algorithm was implemented that populated the physical RAMs by selecting RAM slices one at a time.
Other conventional devices had small, medium, and large physical memories. For these devices, a different clustering algorithm was implemented that automatically optimized the packing of user logical RAMs among the various physical RAMs.
However, all of these conventional devices lacked LUT RAM capability—i.e., the ability to use LUTs to implement user logical RAM. Therefore, no need existed for algorithms that handled balancing logical RAM between physical RAMs and LUT RAM usage.
Yet other tools determined mapping of memory during logic synthesis and then never re-mapped the memory to optimize the memory for a particular implementation.
Furthermore, no known memory mapping algorithms perform optimization on shared blocks of logic and memory following the mapping that occurs during synthesis.
It would be desirable to provide RAM mapping algorithms for shared blocks of memory (that balance between physical RAMs and LUT RAM usage) at later stages of the Computer Aided Design (CAD) flow because RAM mapping at later stages of the CAD flow can take advantage of more accurate information about the device utilization and performance that is obtained following synthesis and make more intelligent mapping decisions.